In the majority of PLL systems, there is an inherent tradeoff between reducing ‘lock in time’ and jitter that results from noise in the reference signal. A narrow band width attenuates small noise from the reference/input signal, thereby resulting in reduced noise and induced jitter at the output. However, reduced bandwidth implies an increase in lock-in-time of the PLL. There have been many approaches used to reducing lock-in-time of PLLs. These include digital/DSP (Digital Signal Processing) methods, dual loop/PLL architectures, feed forward compensation techniques, and variable loop bandwidth methods. In the DSP method, the phase error is fed in to a ‘fast DSP processor’ whose output is then used to adjust the center operating frequency of a VCO (Voltage Controlled Oscillator). Once the error is reduced below some threshold, the VCO voltage from the DSP will be fixed and the PLL loop will take over. In the dual loop/PLL approach, the first loop is used to accomplish a channel select. Since the desired channel is externally selected, the first loop will then quickly lock-in to the desired channel. This channel is then fed to the second PLL loop. In the feed forward method, an estimate of the frequency of the input/reference clock is made which is then used to set the VCO center frequency. Once this is done, the PLL loop can take over. By far the most common approach to reducing lock-in-time involves changing loop parameters. In particular, it involves varying the filter time constants to vary the loop bandwidth. There are also various complicated or otherwise unwieldy techniques for adaptively changing loop bandwidth parameters.
It would be desirable to provide a relatively simple and straightforward approach to varying the loop bandwidth.